When a CMOS device does not perform a switching operation (at a time of a quiescent state), DC current other than leakage current does not flow in the CMOS device. However, when a fault such as a bridge fault is present in the CMOS device, the DC current flows. In the IDDQ test, a power supply current (referred to as a quiescent power supply current or also as an IDDQ current (VDD power supply current Quiescent) is measured. The power supply current flows between power supply terminals (between VDD and GND terminals) in the quiescent state of a chip, which is a device under test. Then, by monitoring abnormal leakage current, screening of a fail chip is performed. After a vector has been applied to the device under test from a tester and then signals have been settled, the quiescent power supply current that flows between the power supply terminals is measured. With respect to the IDDQ test, a description of Patent Document 1 or the like is referred to.
Patent Document 1:
    JP Patent Kokai Publication No. JP-P-2004-170126A